1. Field of the Invention
The present invention relates to semiconductor devices, such as microcomputers, that are provided with an output circuit. More particularly, the present invention relates to a semiconductor device for use in apparatus that perform high-speed data processing such as wireless communication.
2. Description of Related Art
Since a signal obtained by data processing performed in semiconductor devices, such as microcomputers, that are used in various types of apparatus is weak, an output circuit is provided therein for amplifying that weak signal and outputting it. In the semiconductor devices provided with such an output circuit, different tests are conducted for checking the state of the output circuit. Some examples of such tests are a function test for checking whether or not a desired output can be obtained from the output circuit by operating the semiconductor device, an output current test for checking the level of a current that flows through the output circuit when one of the elements constituting it is forced ON, and an output leakage current test for checking the level of a current that leaks from the output circuit when all the elements constituting it are forced OFF.
Conventionally, semiconductor devices provided with a logic circuit for test control have been adopted so that the above-described different tests on the output circuit are conducted by inputting instruction signals indicating the execution of those tests. For example, according to a semiconductor device disclosed in JP-A-H02-232577, a test control signal generation circuit is provided that generates a test control signal from a test control input signal and provides it to different output circuits. With this configuration, a logic circuit that judges which test is required is provided in each output circuit, and, since the test control signal generated from the test control input signal is inputted thereto, it is possible to simplify the logic circuit provided in each output circuit.
Moreover, according to a semiconductor device disclosed in JP-A-H04-373310, an output buffer circuit is formed by connecting two circuits, each composed of serially connected P-channel MOS transistor and N-channel MOS transistor, in parallel, so that a malfunction in the tester caused by switching noise is prevented by using one of two P-channel MOS transistors or one of two N-channel MOS transistors when a function test is conducted. Here, a logic circuit for switching between a function test and normal operation is provided in a stage preceding the output buffer circuit.
Furthermore, according to a semiconductor device disclosed in JP-A-H08-162937, as is the case with the semiconductor device disclosed in JP-A-H04-373310, two circuits, each composed of serially connected P-channel MOS transistor and N-channel MOS transistor, are connected in parallel. The semiconductor device disclosed in JP-A-H08-162937 differs from the semiconductor device disclosed in JP-A-H04-373310 in that the two P-channel MOS transistors and the two N-channel MOS transistors are used when different tests are conducted, whereby a current driving capability thereof is enhanced and the tests can be conducted efficiently. Here, a logic circuit for switching between different tests and normal operation is provided in a stage preceding the output circuit built with the P-channel MOS transistors and the N-channel MOS transistors.
An example of the configuration of a conventional semiconductor device having the function of conducting different tests is shown in FIG. 6. The semiconductor device having the configuration shown in FIG. 6 includes an internal circuit 101 to which data is inputted, a state control circuit 102 to which data processed by the internal circuit 101 is fed, and an output circuit 2 that produces, through an output terminal 1, an output at a high, low, or high-impedance level according to the output of the state control circuit 102. To the state control circuit 102, signals PTEST, NTEST, and HIZ for fixing the output circuit 2 in high, low, and high-impedance states, respectively, and a signal TEST for executing a test function are inputted.
In the semiconductor device configured as described above, when the signal TEST is inputted, the state control circuit 102 is set so as to execute a test function. When the signal PTEST is inputted, control is performed by the state control circuit 102 in such a way that an output signal at a high level is forced to be outputted from the output circuit 2 regardless of the output of the internal circuit 101. Similarly, when the signal NTEST or the signal HiZ is inputted, control is performed by the state control circuit 102 in such a way that an output signal at a low or high-impedance level is forced to be outputted from the output circuit 2 regardless of the output of the internal circuit 101.
In recent years, with an increase in the data processing capacity of wireless communication apparatus or the like, a higher data transfer speed thereof is required. It is for this reason that semiconductor devices, such as microcomputers, incorporated in such apparatus are required to have an enhanced processing capability and output an output signal at higher speed. Some semiconductor devices required to realize such speeding up operate at a frequency of more than 100 MHz (in terms of access speed, less than 10 nanoseconds).
Incidentally, the conventional semiconductor device requires a test circuit for conducting different tests on the output circuit, and therefore an attempt is made to reduce the time and cost of the tests performed by the test circuit. However, as disclosed in JP-A-H02-232577, JP-A-H04-373310, and JP-A-H08-162937, since the test circuit provided in the semiconductor device is built with logic circuits directly inserted in the output circuit, an extra gate delay is undesirably added to the output signal in normal operation by the logic circuits constituting the test circuit.
That is, in the semiconductor device configured as shown in FIG. 6, the state control circuit 102 is needed to achieve a test function and is provided separately from the internal circuit 101. Thus, in a case where this conventional semiconductor device is used, it is necessary to provide logic circuits inside it for performing a calculation operation on different signals by which the test circuit such as the state control circuit 102 achieves a test function. As a result, the test circuit such as the state control circuit 102 is affected by a gate delay produced by the logic circuits provided for achieving a test function. This undesirably hampers the speeding-up of data output.
In view of the conventionally experienced problems described above, an object of the present invention is to provide semiconductor devices provided with an output circuit that can conduct different tests without the need of directly inserting a test circuit in a path along which an output signal is transmitted.